With reduction in size and weight of electric apparatuses for portable phones, portable information terminals, etc., the density of electric equipments to be mounted to these apparatuses has been increasing. In response, semiconductor devices are more and more integrated, and a size of a chip for each semiconductor device has been increasing. On the other hand, smaller processing sizes are demanded to realize lighter weight, thinner and smaller size semiconductor devices, and changes have been made in design rule indicative of the microscopic level of semiconductor devices for smaller size semiconductor devices.
A semiconductor device cut out from a wafer is made up of an active region formed inside and a pad region formed on a surface of a semiconductor device. The active region is made up of an operating region where a transistor, a diode, and other semiconductor element, etc., are formed, and a wiring region where metal wirings are formed, such as an aluminum (Al) wiring, etc., for connecting the semiconductor elements to a predetermined part in the semiconductor device to conduct these semiconductor elements. A pad region is provided for applying a voltage or a signal from an external section of the semiconductor device to an active region, and from the active region to the external section of the semiconductor device. This pad region is a region in the bump to be connected to an external section of the semiconductor device, and a bonding pad is formed in the bump. For a liquid crystal driver as an example of the semiconductor device, the method of mounting an IC (Integrated Circuit) chip on a flexible print circuit, a so-called COF (Chip On FPC (flexible print circuit)) mounting method is generally adopted. For the liquid crystal drivers, a pad region is a region for inputting and outputting signals for liquid crystal driving.
As an example, the COF mounting method will be explained in reference to FIGS. 7(a) and 7(b).
FIG. 7(a) shows a semiconductor element (IC chip) 301, terminal electrodes 302 for input and output formed on the surface of the semiconductor element 301, bonding pads 303 formed on the terminal electrodes 302 for input and output, an insulating film substrate 304, a metal wiring pattern 305 formed on the surface of the insulating film substrate 304 and a bonding tool 306.
Generally, the semiconductor element 301 includes terminal electrodes 302 for input and output on its surface, such as an aluminum pad, etc., and on each of these terminal electrodes 302 for input and output, a bonding pad 303 is formed in a thickness of 10 μm to 18 μm. On the other hand, a flexible print wiring substrate having formed thereon the semiconductor element 301 has the metal wiring pattern 305 formed on the insulating film substrate (film substrate) 304 mainly made up of a plastic insulating material such as polyimide resin, polyester, etc.,
In the COF mounting system, generally, positioning of the semiconductor element 301 having formed thereon bonding pads 303 is performed with respect to the metal wiring pattern 305 formed on the insulating film substrate 304 as illustrated in FIG. 7(a). Namely, the bonding pad 303 is positioned so as to match a predetermined position on the metal wiring pattern 305.
The metal wiring pattern 305 is made of an electrically conductive material mainly made up of cupper (Cu), and the surface of the electrically conductive substance is plated with tin (Sn) or gold (Au). For the metal wiring pattern 305, an inner lead, an outer lead, an intermediate lead may be adopted. However, differences in types of the metal wiring pattern 305 are not significant, and detailed explanations thereof shall be omitted here.
The insulating film substrate 304 is formed in a band shape, and is called a tape carrier. Along both sides, feed holes are formed at predetermined intervals, so that the insulating film substrate 304 can be moved in a lengthwise direction.
After carrying out the positioning between the insulating film substrate 304 and the semiconductor element 301, the bonding pad 303 and the metal wiring pattern 305 formed on the surface of the insulating film substrate 304 are subjected to the thermo compression bonding using the bonding tool 306, thereby bonding the semiconductor element 301 to the insulating film substrate 304 as shown in FIG. 7(b). This connection method is generally called the inner lead bonding (ILB).
After carrying out the ILB, although not shown, the semiconductor element 301 is sealed with resin such as a material of epoxy resin, silicone resin, etc. To be sealed with resin, specifically, resin is applied from a nozzle over a semiconductor element, and the resin thus applied is hardened with an application of heat such as the reflow system. Thereafter, the portion having mounted thereon the semiconductor element 301 is cut out by the insulating film substrate 304 to be mounted to a liquid crystal display panel as each semiconductor device (integrated circuit).
In the following, the method of packaging the semiconductor device will be explained.
In a conventional semiconductor device, a bonding pad is not formed in the operating region but formed in a circumferential portion of the operating region so that a mechanical pressure when bonding the Au bump to the external connection terminal or stress due to thermal stress, etc., are not applied to the operating region via the bonding pad. Incidentally, bonding pads, for liquid crystal drivers, etc., are generally formed at pitches (intervals) of 50 μm to 100 μm, and are formed in rectangular shape of 40 μm×90 μm, although this size may vary depending on pitches.
In recent years, semiconductor devices have tendencies towards complicated structures of metal patterns connecting elements for a higher density and integration, and generally a multi-layered structure of laminating a plurality of wiring layers is adopted, which in turn increases the number of terminals connecting the semiconductor device to the external terminal up to 500. Therefore, when the region of the bonding pad (pad region) as terminals is formed outside the operating region, the area of the region other than the operating region increases with an increase in number of terminals, and the semiconductor device becomes larger in size, which hinders the lighter weight, thinner and smaller size portable phones, PDAs (Personal Digital Assistant), etc.
In response, a method of forming a bonding pad right above the operating region of semiconductor device has been proposed to realize a smaller size semiconductor device. This method is called “area pad”, and hereinafter, the bonding pad formed right above the operating region of the semiconductor device is referred to as an area pad.
Conventional techniques for the area pad will be explained.
The area pad in a semiconductor device of double layer wiring structure is disclosed, for example, by the US Laid-Open patent publication No. 2002-0043723 (published on Apr. 18, 2002) corresponding to Japanese Laid-Open Patent Publication No. 2002-198374/2002 (Tokukai 2002-198374) (published on Jul. 12, 2002) (hereinafter referred to as the first conventional example), and this area pad will be explained in reference to FIG. 8.
As illustrated in FIG. 8, the semiconductor device is made up of a silicone substrate 101 including an operating region where the semiconductor element 120 is formed, a first wiring layer 102 (a part of the wiring region) formed on the silicone substrate 101, the first wiring layer 102 being electrically connected to the operating region, a second wiring layer 107 at above the first wiring layer 102 (a part of the wiring area) via an interlayer insulating film 106, and a bonding pad 112 to be electrically connected to the external section formed above the second wiring layer 107 so that at least a part of the bonding pad 112 is located right above the operating region. The bonding pad 112 includes a barrier metal 113 and a gold bump 114. This barrier metal 113 is formed in the bottom end portion of the boding pad 112 in a vicinity of a bonding face of the bonding pad 112 with the second wiring layer 107. The semiconductor element 120 is an MOS (Metal Oxide Semiconductor) transistor, which is made up of impurity diffusion layer which functions as a source region formed on the surface layer of the silicone substrate 101, and an impurity diffusion layer which functions as a drain region.
The structure of the semiconductor element 120 is not directly to do with characteristic features of the present invention (to be explained later), and detailed descriptions will be omitted here, and only the structures of other elements will be explained. Specifically, the respective structures of the first wiring layer 102 electrically connected to the operating region and the structure of the elements formed above the first wiring layer 102 will be explained.
The first wiring layer 102 has a single layer or multi-layered structure made up of a conductive member such as aluminum, etc. The first wiring layer 102 is formed on the operating region via the insulating film, and includes a plurality of wires. Some of the plurality of wirings of the first wiring layer 102 are connected to the operating region via the contact hole. Above the first wiring layer 102, formed is an interlayer insulating film 106 for insulating the first wiring layer 102 and the second wiring layer 107 (to be electrically disconnected).
The interlayer insulating film 106 is made up of a silicone oxide film 106a, an SOG film 106b and a silicone oxide film 106 which are laminated in this order from the side of silicone substrate 101. The SOG film 106b is provided for making smoother the protrusions and recessions formed on the surface due to the first wiring layer 102. The silicone oxide films 106a and 106c are formed in thickness of, for example, 500 nm.
The second wiring layer 17 is also made up of a conductive member such as aluminum, etc., and has a single layer or multi-layered structure as in the first wiring layer 102. The second wiring layer 107 is formed right under the bonding pad 112, and includes a plurality of mutually insulated wirings. In the figure, wirings 107a, 107b and 107c are formed as these plurality of wirings. Among these wirings 107a to 107c, the wiring 107a is connected to the bonding pad 112. On the other hand, the wirings 107b and 107c are formed in a form of a layer in such a manner that a protective film 108 and a polyimide film 110 are formed between these wirings 107b and 107c and the bonding pad 112. The protective film 108 and the polyimide film 110 have openings 109 and 111 respectively to be connected to the bonding pad 112 and the wiring 107a. The wiring 107b is connected to a part of the first wiring layer 102 via a via-hole of the interlayer insulating film 106.
The bonding pad 112 is connected to the wiring 107a of the plurality of wirings of the second wiring layer 107 via the openings 109 and 111. Here, the contact face of the wiring 107 connected to the bonding pad 112 is significantly smaller than an area of the flat face of the bonding pad 112 (the area projected in an orthogonal direction on the silicone substrate 1). With this structure, it is possible to provide wirings other than the wiring 107a, i.e., the wirings 107b and 107c in the region directly under the bonding pad 112 other than the contact face between the second wiring layer 107 and the bonding pad 112. Incidentally, in the prior art semiconductor device before the first conventional example provided with the area pad is disclosed, the area of the contact face between the wiring layer and the bonding pad (protruded electrode) is substantially the same as the cross sectional area of the bonding pad. In contrast, in the semiconductor device of the first conventional example, the degree of freedom of the wirings of the second wiring layer 107 is increased by reducing the contact face between the second wiring layer 107 and the bonding pad 112.
The protective film 108 and the polyimide film 110 are provided for reducing the interval between the wirings 107b and 107c, and the bonding pad 112. The protective film 108 and the polyimide film 110 are provided between the bonding pad 112 and the second wiring layer 107 for insulating (electrically disconnecting) them in regions other than the contact face between the second wiring layer 107 and the bonding pad 112 including the region between the wirings 107b and 107c and the bonding pad 112. The polyimide film 110 is formed so as to be gradually sloped from the contact face between the second wiring layer 107 and the bonding pad 112 to the outer circumferential portion of the bonding pad 112. This polyimide film 110 serves as an insulating film for electrically insulating the wirings 107b and 107c of the second wiring layer 107, and the bonding pad 112, and also serves as a buffer that reduces a stress due to load and pressure, etc., applied when mounting, for example, by the COF to the bonding pad 112 and prevents the first wiring layer 102 or the second wiring layer under the bonding pad 112 from being damaged.
By the way, the foregoing conventional semiconductor device wherein the first wiring layer and the second wiring layer are formed above the operating region where the semiconductor element is formed, and the bonding pad is formed at above the second wiring layer has such problem that an insulating film between the bonding pad and the second wiring layer is cracked by the loads applied to the bonding pad.
FIG. 9 schematically shows the portion above the second wiring layer of structure of the semiconductor device. In FIG. 9, a second wiring layer 202 is formed in the region right under a bonding pad 201. The second wiring layer 202 is made up of a pad metal 203 connected to the bonding pad 201 to have the same potential with the bonding pad 201, and other wirings 204 insulated from the bonding pad 201 to have different potentials from that of the bonding pad 201. The pad metal 203 corresponds to the wiring 107a in FIG. 8. Furthermore, between the second wiring layer 202 and the bonding pad 201, formed is an inorganic insulating film 201 for insulating the bonding pad 201 from other wirings 204. An inorganic insulating film 205 on the pad metal 203 is an opening for the conduct between the bonding pad 201 and the pad metal 203.
According to the semiconductor device of the foregoing structure, on the inorganic insulating film 205 between the second wiring layer 202 and the bonding pad 201, protrusions and recessions are formed according to the shape of the second wiring layer 202. Furthermore, the protrusions and recessions formed on the inorganic insulating film may cause a crack 211 in the inorganic insulating film 205 with an applied stress from above via the bonding pad 201, which may causes moisture to be seeped, and a corrosion due to the current applied in the portion having moisture seeped, which may result in disconnection. Furthermore, the moisture seeped in a crack 211 becomes a medium, and between the bonding pad 201 and the portion to be insulated from the bonding pad 201 is shorted, or a leak inferior occurs in that the current flows in the part not intended.
In particular, in the case where other wirings 204 are formed in the region right under an edge 201a of the bonding pad 201, or in the region right under the edge 208a of an inner lead 208 when carrying out the ILB of the semiconductor device, it is known that the a crack 211 is liable to be generated in either one or both of the region right under the edge 201a and the region right under the edge 208a. The stress due to the stress from above is most liable to be applied onto the edge 201a of the bonding pad 201 when carrying out the COG (Chip On Glass) mounting, and the COF mounting.
As an example of the COF mounting, it is confirmed by the experiment that when carrying out the ILB with respect to the bonding pad 201 in size of 40 μm×90 μm, with an applied load in a range of 150 N to 200 N at temperatures in a range of 380° C. to 430° C., the bonding pad 201 is expanded in all directions by around 2 μm. Namely, the stress is applied not only from above but also in the lateral directions. The expanded region 201 shown in FIG. 9 indicates the expanded region of the bonding pad 201 in the lateral directions.
Therefore, when mounting, the stress is applied in regions of the bonding pad 201 outside the edge 201a by around 2 to 3 μm, both from above and in lateral directions, and therefore, in the case where other wirings 204 are formed in the region right under the edge 201a and in the region right under the edge 201a before mounting to 2 μm to 3 μm outside the region, the crack 211 is liable to be generated.
Furthermore, when carrying out the inner lead bonding like the case of the COF mounting, for the structure wherein the other wirings 204 are formed in regions right under the edge 208a of the inner lead 208 or regions outside a vicinity of the regions right under to edge 208, a crack may be caused.
As described, irrespectively of the mounting method, the TCP, the COF or the COG, in the case of carrying out the package of the semiconductor device, by electrically connecting the bonding pad 201, the inorganic insulating film 205 is liable to be cracked by the stress. Incidentally, when packaging using the inner lead 208 such as the TCP, the COF, etc., with the stress from the inner lead 208, the inorganic insulating film 205 is liable to be cracked.
In order to avoid the generation of crack, as illustrated in FIG. 8, in the first conventional example, an organic high polymer film such as a polyimide film 110, etc., is formed on the part of the insulating layer between the bonding pad 112 and the second wiring layer 107, to reduce an impact on the second wiring layer 107 from the bonding pad 112. However, the polyimide film 110 is formed at above the second wiring layer 107, and the polyimide film 110 is inclined from the contact face between the second wiring layer 107 and the bonding pad 112 to the outer circumference of the bonding bad 112, thereby generating a new problem of contact inferior.
Incidentally, the barrier metal 113 is formed on the interface between the gold bump 114 and the pad metal 4 and the polyimide film 110, and the polyimide film 110 is made up of an organic insulating material, and has small adhesiveness with the barrier metal 113. As a result, a problem is presented in that the bonding pad 112 is peeled by the external pressure from the interface between the barrier metal 113 and the polyimide film 110.